Implementing the V flag requires a new flip-flop as shown in blue on Figure 1, and logic in the ALU block to drive it. Note that the V flag is written by the same instructions that would write to the C flag (any instructions that use the ALU adder). Figure 2 shows an 8 bit adder split into its 7 least significant bits and its sign bit. When the carry bits c and c′ are different there is a two’s complement signed overflow. For why this is true see the mini-lecture on overflow.
FIG 1
FIG 2: EEP1 Signed Overflow Logic
<aside> ✅ Task 1.
Implement a V (signed overflow) output from the ALU by replacing the ALU 8 bit binary adder by a 7 bit and 1 bit adder and implementing logic as in Figure 2.
Task 2.
Add a V flipflop to your design connected as shown on Figure 1.
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Basically, we’ve simply split the 8 bit adder into a 7 bit and a 1 bit adder. This way we can check individual Couts to see if overflow happens or not.
If there was a change in Cout at the end of the operation (8th bit) , it means that whatver mathematical operation that occured has experienced some carry over or answer which cannot be expressed within 8 bits range. This is noted of by G1, or the XOR gate in the top right connected to V.
This V follows the flip-flop design as other flags such as the Carry flag.
V-flipflop all ready to be fed into the decode block.
Once we’re done, we exit with an error – totally normal, this is supposed to happen as ALU has gained another output V, which is yet to be routed into the design.
<aside> ✅ Task 3.
In the decode sheet change the J output logic so that all 13 jump instructions except JSR/RET
are implemented.
Task 4.
The easiest way to check your logic is using the step simulator on the decode block and manually
changing inputs. Check that each instruction group correctly implements its condition and that setting N=1 inverts the condition.
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decode needs to be modified for the new instructions.
The thing is, decode does all the computing within its block and makes the decision whether the next step is to contain a jump or not.
We can create a special block called jumpdecode to process the inputs of the N, C, Z flags and output whether a jump occurs or not.
We’ll work on implementing all except for the JSR/RET group.
Explain how, if J can be implemented correctly for all of the instruction bit N=0 instructions, one additional XOR gate could be used to implement N=1 instructions as well. See one problem this causes for non-jump instructions, and how to solve it.