Testing the EEP1 Design

Before starting work on the rest of EEP1, we check that it jumps correctly by running the EEP1_test.ram code.

0 JMP #3 // JUMP OVER TERMINATION POINTS // SUCCESS (SELF−LOOP)
1 JMP #1
2 JMP #2 // FAIL (SELF−LOOP)
3 JNE #5 // SHOULD JUMP (Z=0 INITIALLY)
4 JMP #2
5 JPL #7 // SHOULD JUMP
6 JMP #2
7 JCC #12 // SHOULD JUMP
8 JMP #2
9 MOV R0, #0X45
10 RET#2 //USEIMM8 = 2SO IF RET DOES NORMAL JUMP IT IS A FAILURE 
11 JMP#2 //IF RET DID NOT JUMP WE END UP HERE
12 MOV R0, #0X10
13 ADD R0, #0X20
14 SUB R0, #0X30
15 JNE #2
16 MOV R4, #0X10
17 MOV R0, #0X20
18 ADD R4, R0, #0X0
19 JCS #2
20 SUB R4, #0X30
21 JNE #2
22 JCC #2
23 MOV R5, R4, #−1
24 ADC R5, #1
25 JCC #2
26 JEQ #2
27 MOV R0, #0XFF
28 MOV R1, #0
29 SUB R0, R1
30 JGE #2
31 JLS #2
32 MOV R0, #0
33 MOV R1, #0XFF
34 SUB R0, R1
35 JLT #2
36 JHI #2
37 MOV R0, #0XFE
38 SUB R0, R1
39 JGE #2
40 JHI #2
41 JSR #9 // SHOULD GO TO ADDRESS 3 AND THEN RETURN WITH R0 = 0X45 42 SUB R0, #0X45
43 JNE #2 // THE SUBROUTINE CODE DID NOT SEEM TO EXECUTE?
44 JMP #1 // SUCCESS IF WE GET HERE!

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Terminates on PC = 1 eventually. Phew! This means that all of our code and schematics are working as intended.

Reflections on Boolean logic description

FIG 1.1

FIG 1.2

Hardware compilers optimise Boolean logic
jumps schematic uses Issie gates to determine J, compare to FIG 1.1
FIG 1.2 shows Verilog HDL for the jumps circuit
On a schematic, you could attempt to improve readability by defining, in a separate sheet, an 8 input multiplexor component. The multiplexor 3 bit select is then driven by OPCJMP. This would come at the cost of losing labels indicating each of the 8 jump types, so it is not obviously a better solution. [omitted]

Explaining the Boolean expression:

I[14] and I[15] need to be both 1 to be considered a jump instruction.
I[8] is XOR-ed with a sum of products of conditions needed for a jump instruction.
Let’s move on to the bracketed portion containing sums of products, which are the boolean conditions for the instructions:

Assuming I[8] = 0:

OPCJump	Instruction	Flags	Conditions
000	JMP	None	(!P)(!Q)(!R)
001	JNE	!Z	(!P)(!Q)(R)(!Z)
010	JCS	C	(!P)(Q)(!R)(C)
011	JMI	N	(!P)(Q)(R)(N)
100	JGE	(!N) ⊕ V	(P)(!Q)(!R)((!N) ⊕ V)
101	JGT	((!N) ⊕ V)(!Z)	(P)(!Q)(R)((!N) ⊕ V)(!Z)
110	JHI	C!Z	(P)(Q)(!R)(C)(!Z)
111	JSR		PQR

Flags don’t get inverted, only the OPCJUMP does.

Jump occurs when I[8] = 0 and any one of these boolean conditions evaluate to true. Only one is needed as we’re doing sums of products, for the entire bracket to evaluate true.

When I[8] = 1 , for J to evaluate as True, all the conditions in the table above must NOT be satisfied. The only 8 other possible outcomes are the inverse of these instructions, and there will be one of the inverse instructions (JEQ, JCC, JPL, JLT, JLE, JLS, RET) which will have satisfied boolean conditions.

There is obviously a lot of inductive logic and reasoning missing here, but when you enumerate all the possible outcomes and do not see it in the table above, it only exists in the inverse instructions (see below).

OPCJump	Instruction	Flags	Conditions
000	JMP	None	(!P)(!Q)(!R)
001	JEQ	!(!Z)	(!P)(!Q)(R)!(!Z)
010	JCC	(!C)	(!P)(Q)(!R)!(C)
011	JPL	(!N)	(!P)(Q)(R)!(N)
100	JLT	!((!N) ⊕ V)	(P)(!Q)(!R)!((!N) ⊕ V)
101	JLE	!(((!N) ⊕ V)(!Z))	(P)(!Q)(R)!((!N) ⊕ V)(!Z)
110	JLS	!(C!Z)	(P)(Q)(!R)!(C)(!Z)
111	RET		PQR

Implementing SBC/AND/XOR/LSR

T1

<aside> ✅ Task 1. Change the logic in the decode ****sheet so that F(2:0) and CEn is correct for the SBC instruction as well as ADD, SUB, ADC as in Figure 1.1.

</aside>

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FIG 1.1